The Peripheral Component Interconnect Express (PCIe) computer bus standard is used for computer expansion cards and graphic cards. PCIe is both full duplex and point-to-point. PCIe is a layered protocol and has a physical layer, a data link layer and a transaction layer.
In the physical layer, a connection between any two PCIe devices is known as a link. Each link is built up from one or more lanes. More lanes allow for higher rate of data flow through a link.
The data link layers provide sequencing for Transaction Layer Packets (TLPs). The TLPs are generated by the transaction layer. The data link layer uses acknowledgments (ACKs) and negative acknowledgements (NAKs) to guarantee delivery of TLPs. ACKs and NAKs are communicated by data link layer packets (DLLPs) that are low level packets. DLLPS also are also used for power management functions.
PCIe utilizes link level credit-based flow control. In link-level credit-base flow control, credits are based on the amount of space available in receive buffers that receive data into the transaction layer from the data link layer. Each device on a link advertises an initial credit limit to the device on the other end of the link. A device will only send a TLP across the link when sending the TLP will not exceed the current credit limit for the receiving device. Upon sending a TLP, the sending TLP will subtract the number of credits used by the TLP from the current credit limit. When the receiving device finishes processing the TLP from its receive buffer, the receiving device will signal a return of credits to the sending device. The sending device then adds the number of credits returned to the current credit limit. Counters used to count credits are modular and modular arithmetic is used to determine a current credit limit. DLLPs are used to communicate flow control information between two connected devices.
When using link level credit-based flow control, the latency of credit return does not affect performance as long as the credit limit is not encountered.